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| this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. june 2014 docid025319 rev 1 1/69 L99LD01 high efficiency constant current led driver for automotive applications datasheet - preliminary data features ? automotive qualified ? constant current operation ? current led settable by external sensing resistor and adjustable via spi ? converter switching frequency adjustable by external resistor (r sf ) ? emc reduction by internal spread spectrum dither oscillator ? low frequency pwm dimming operation. ? maximum input current limiter ? maximum switching duty cycle limiter ? slope compensation adjustable by external resistor (r9) ? battery overvoltage shut down protection (ext. r3, r4 resistors required) ? led chain ov detection (ext. r5, r6) ? multiplexed output for monitoring and control of led temperature (external ntc resistor required), voltage of led chain, and low frequency pwm ? spi communication serial interface transceiver (sdi, sdo, sck, csn) ? regulated output for micro supply 5 v 2 % -20 ma ? parameter programming and settings of internal memory registers by the dedicated spi interface: ? led current reference adjusting ( 66.7 %) ? maximum input current limiter reference adjusting ( 55.5 %) ? random dither frequency sweeping, modulation frequency and deviation percentage ? power on reset pin output ? esd protection applications automotive day time running light, led headlamps description L99LD01 is a complete constant current dc?dc converter led driver, manufactured in a bcd5s 70 v technology and assembled in a lqfp32? package. the device is designed to be used in boost, buck- boost and fly back converter topologies. an internal random dither oscillator works in low frequency modulation, allowing the rf spectrum of the switching frequency to spread so to reduce emc emissions. the slope compensation ensures good converter loop stability whatever is the duty cycle needed by the application. the converter is able to work either in full power mode or in low frequency dimming mode. the device includes an internal low drop voltage regulator, that can be used to supply a microcontroller, and a reset pin , that is useful for resetting the microcontroller at the start up and every time that the regulated output voltage falls down below an established voltage threshold. max v batt 40 v operation supply battery voltage v batt 5.6 - 24 v oscillator frequency range 100 - 500 khz lqfp32 7x7mm lqfp32 7x7mm www.st.com
contents L99LD01 2/69 docid025319 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 operation with an external microcontroller . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 stand alone operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.3 start-up fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.4 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.5 software limp home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.6 limp home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 protections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.1 led current adjust and temperature control . . . . . . . . . . . . . . . . . . . . . 16 2.2.2 slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.3 led chain overvoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.4 battery overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.5 regulators thermal shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.7 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.8 standby and wake up by enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.9 frequency setting and dither effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.10 start up led overvoltage management . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.11 programming the over/under voltage threshold . . . . . . . . . . . . . . . . . . . 27 2.2.12 input overvoltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 spi functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1 serial peripheral interface (st spi standard) . . . . . . . . . . . . . . . . . . . . . . 31 3.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.1 sdi, sdo format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.2 global status byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.3 operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4 address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.5 control registers (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.6 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 docid025319 rev 1 3/69 L99LD01 contents 3 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6 spi electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.2 lqfp32? package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 list of tables L99LD01 4/69 docid025319 rev 1 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. limp home mode: recovery paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. suggested k l value and overvoltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 4. command byte (8 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5. input data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 6. global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7. output data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10. ram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 11. rom memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 12. internal oscillator frequency deviation settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 13. internal oscillator frequency modulation settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 14. watchdog timer status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 16. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 17. vs and v cc1 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 18. v cc2 and c5v pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 19. nres and lmode pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 20. g1 driver 1 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. g2 pin characteristics (driver2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 22. converter oscillator and rsf pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 23. pwm_l, pwm, mout pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 24. isense+, isense- pin, and o.t.a. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 25. sc pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 26. vled pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 27. inp_ov pin characteristics (input overvoltage shut down). . . . . . . . . . . . . . . . . . . . . . . . . 52 table 28. ntc pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 29. enable, lhm pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 30. power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 31. watchdog and timers parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 32. spi dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 33. spi ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 34. spi dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 35. lqfp32? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 36. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 37. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 docid025319 rev 1 5/69 L99LD01 list of figures 5 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. connection diagram (top view ? not in scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. operating modes, main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. normal start up vs v s ramp up and v cc1 voltage dips. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. v cc1_fail or v cc1 reset under voltage (v s >v smin ) at start up . . . . . . . . . . . . . . . . . . . . 14 figure 6. v cc1 reset under voltage at start up (v s < v smin ) and fast v s ramp down . . . . . . . . . . . . 15 figure 7. slow vs ramp down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. internal structure of the slope compensation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. operation with a standalone lin and enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. operation with pm device and enable (fso active low) . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. internal structure of main converter oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. converter frequency range vs r sf and i rsf vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. correct start up with no led overvoltage failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. led overvoltage after t dstart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. device behavior in case the low to high transition of pwm_l signal happens after t dstart expiration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. led overvoltage event not caused by a vs overvoltage event . . . . . . . . . . . . . . . . . . . . . 26 figure 17. led overvoltage detection due to a possible battery vs overvoltage . . . . . . . . . . . . . . . . 27 figure 18. behavior of led overvoltage recovery bit with low on-time of pwm_l . . . . . . . . . . . . . . . 27 figure 19. led chain overvoltage thresholds settings. an example for boost and fly back converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 20. input overvoltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 21. clock polarity and clock phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 22. spi global error information output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 23. spi write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 24. spi read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 25. spi read and clear operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 26. spi read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 27. principle of the wd_status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 28. voltage and current conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 29. spi timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 30. spi input and output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 figure 31. spi maximum clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 32. nres pin open drain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 33. handshake procedure at start up with microcontroller on board . . . . . . . . . . . . . . . . . . . . 58 figure 34. boost application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 35. fly back application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 36. buck-boost application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 37. stand alone application example for boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 38. reverse battery protection: an example for boost topology . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 39. external mos required during pwm dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 40. lqfp32? package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 block diagram and pin description L99LD01 6/69 docid025319 rev 1 1 block diagram and pin description figure 1. block diagram figure 2. connection diagram (top view ? not in scale) ) ) 4 6 5 , 6 ( 1 6 ( , 6 ( 1 6 ( 2 7 $ 5 & & 2 0 3 ' 5 , 9 ( 5 3 : 0 & r p s 1 7 & 5 6 ) 0 d l q 2 v f l o o d w r u , 6 1 , 6 3 9 6 9 & & 9 5 ( ) 9 / ( ' 9 / 5 ( ) 2 9 % d w w b 2 9 6 : 0 $ ; , 1 3 & 8 5 5 ( 1 7 ' x w \ 0 d [ / $ p s / ( ' 2 y h u 9 r o w d j h ' h w h f w l r q 6 7 2 3 b & 2 1 9 / + b 2 ) ) 6 w d w h 0 d f k l q h ) r u 3 d u d p h w h u 6 h w w l q j v ' l d j q r v w l f : ' * 1 ' * $ q d o r j 0 8 ; 5 d q g r p l f ' l w k h u / 6 & r p s ' 5 , 9 ( 5 3 : 0 b / * ( ; 7 b 9 & & & k d u j h 3 x p s ( 1 b 1 7 & * 1 ' 6 w g e \ / ( ' & x u u h q w $ g m x v w 1 7 & & r q w u r o 9 1 7 & b 7 + / 0 2 ' ( 9 , / 0 2 ' ( & b ' l v f k 9 r o w d j h 5 h j x o d w r u % d q g j d s 5 h i 9 r o w d j h 5 h j x o d w r u 9 & & / + b 2 1 6 ' , 6 ' 2 3 : 0 6 & . & 6 1 0 2 8 7 , 1 3 b 2 9 3 : 0 b / 1 5 ( 6 ( 1 $ % / ( / + 0 & 9 6 / 2 3 ( b $ ' - 6 & * 1 ' 2 6 & b 5 $ 0 3 2 6 & b 5 $ 0 3 % d w w b 2 9 & 3 % ' 3 b 9 / ( ' b 2 & / ( ' b 2 & 7 : 7 : , 1 7 & ( ; 7 b 9 & & ( " 1 ( $ ' 5 / 0 2 ' ( * 1 ' 1 7 & 5 & & 2 0 3 ( ; 7 b 9 & & , 1 3 b 2 9 3 : 0 / + 0 6 & ( 1 $ % / ( 9 6 * 1 ' 5 6 ) , 6 1 , 6 3 9 & & 3 : 0 b / 6 ' , 6 ' 2 6 & . 9 & & & 6 1 0 2 8 7 1 5 ( 6 3 * 1 ' * & 9 , 6 ( 1 6 ( , 6 ( 1 6 ( 9 / ( ' * & 3 % - 2 ' 1 ( " 1 ( $ ' 5 docid025319 rev 1 7/69 L99LD01 block diagram and pin description 68 table 1. pin description pin number pin name function 1v cc1 5 v internal voltage regulator 1 output (external capacitor req.) 2 nres reset i/o pin; active low 3 pwm_l logic low frequency pwm input 4 sdi serial spi data input 5 sdo serial spi data output 6 sck spi clock 7 csn chip select not 8 mout multiplexed data output pin 9 ext_vcc internal/external up supply voltage programming pin (1) 1. in case of externally supplied microcontroller, attach this pin to its external supply voltage pin. 10 inp_ov battery overvoltage programming pin 11 pwm low frequency pwm input (battery compatible) 12 lhm limp home mode input pin 13 lmode switch input pin (connect to gnd if led drop voltage is referred to gnd or open (5 v) if led drop is referred to v s ) 14 gnd2 gnd of controller 15 ntc output for external n.t.c. resistor 16 rc comp external r c compensation network 17 vled input for led chain overvoltage detection 18 cpb charge pump buffer capacitor 19 g2 gate 2 output for external pmos m2 20 i sense- negative terminal of the led sense resistor 21 i sense+ positive terminal of the led sense resistor 22 c5v output for 5 v buffer capacitor 23 pgnd power ground 24 g1 gate 1 output for external pmos m1 25 v cc2 10 v voltage regulator 2 output (ext. capacitor required) 26 isn negative terminal of the shunt resistor 27 isp positive terminal of the shunt resistor 28 gnd1 gnd of controller 29 enable enable pin 30 vs supply voltage input pin 31 sc slope compensation setting resistor 32 rsf oscillator frequency setting resistor functional description L99LD01 8/69 docid025319 rev 1 2 functional description 2.1 operating modes the device is able to work both with a microcontroller and without it (stand alone configuration). 2.1.1 operation with an external microcontroller this way allows parameters to be adjusted and checked by means of the spi interface. the adjusted device parameters, stored, i.e., inside the micro eeprom, can be loaded into device internal registers after the start up phase. by means of a small 8 pins microcontroller it is possible to implement the following functions: ? parameters setting: ? led current level and maximum input current limit can be adjusted according to the application, the led characteristic and spreads ? dither oscillator parameters as random, frequency modulation and deviation percentage can be programmed ? flexible pwm operation with duty cycle and frequency managed by the microcontroller ? diagnostic feedback: ? fault condition is sent to the micro when the csn pin is pulled down ? advanced led monitoring: ? led voltage drop and temperature are multiplexed and sent to the microcontroller through the dedicated mout pin in order to monitor the selected parameter with the a/d of the microcontroller. the multiplexer is driven through a spi command. this function allows a sophisticated control of the led status. for example, as an alternative to the default overvoltage detection, it is possible to monitor the led drop voltage, reduced by the external r5/r6 resistor divider. so taking into account the spread and temperature influence on the led voltage drop, the microcontroller is able to detect if there is one or more led shorted. furthermore, it is possible to monitor the led chain temperature, by means of the voltage feedback through the dedicated ntc pin. the temperature limit control, operated by the device by default, can be disabled via the spi and the voltage applied on the ntc pin can be sent back to the microcontroller via the multiplexed output, mout, so allowing the microcontroller itself to control the led chain either acting on the internal current led register or reducing the low frequency pwm duty cycle. ? in case of v r1 over temperature, its output will be switched off, the device enters in limp home mode and a failsafe bit will be set in the internal status register (see details in the following paragraph). in order to restart the normal operation, so clearing the corresponding status register bit, the v s or enable voltage has to be switched off and then on. the mentioned bit can be cleared by the microcontroller only when it is external supplied. docid025319 rev 1 9/69 L99LD01 functional description 68 2.1.2 stand alone operation the device operates with default parameters. the overall tolerance depends on the internal references precision and the external resistors tolerance. in details: ? led current via external sensing resistor: ? maximum input current via an external shunt resistor. ? oscillator dither effects are set to its default parameters; a low level on the sdi allows disabling the function. ? low frequency dimming operation is allowed either by pwm pin or by logic level pwm_l input pin. connecting the pwm control pin to the supply voltage via a resistor divider, allows the converter to be synchronized to the low frequency pwm generated, i.e., from the smart junction box. ? connecting the mout pin, which by default provides a logic level image of the control input, to the pwm_l input, it is possible to drive the led according to the pwm frequency and duty cycle of control. (see application circuit of figure 38 ). ? in case of v r1 over temperature, its output will be permanently switched off. the device still continues to work in normal mode but with v r1 =off. the L99LD01 can operate in 4 different modes: ? start-up fail ? normal mode ? software limp home ? limp home after the power on reset, the device stays in start-up phase until v cc1 reaches a specified threshold, v cc1_th . then the device enters in normal mode either with microcontroller or standalone, depending on the voltage level on the n reset pin. note: the information about the operation with microcontroller or standalone is latched until a new power on reset. if v cc1 does not reach both v cc1 fail and v cc1_th thresholds within a given delay or if a v cc1 over temperature event occurs, the device enters in a corresponding state. 2.1.3 start-up fail the device enters this mode in case a v cc1 under voltage event occurs during start-up phase and v s < v smin , provided that a microcontroller is detected. in this case v cc1 is turned off. if v s remains below v smin , then the converter is switched off. if v s rises above v smin , the converter behaves according to the pwm_l pin. i led 150 mv/r sense = functional description L99LD01 10/69 docid025319 rev 1 2.1.4 normal mode ? normal mode with microcontroller: the device enters this mode after a successful start up (v cc1 > v cc1_th ) and a microcontroller is detected. the device keeps this mode as long as the watchdog is retriggered before a timeout event. ? normal mode in standalone configuration: the device enters this mode if a standalone configuration is detected, independently from v cc1 errors. the L99LD01 keeps this mode even in case of watchdog timeouts. in both cases, the converter behaves according to the pwm_l pin. 2.1.5 software limp home this device enters software limp home mode in case the lh_sw bit is set (see section : control registers 3 ). the control registers are set to their default values, with the exception of the lh_sw bit, which remains unchanged. the converter behaves according to the signal on the lhm pin: ? turned on if a high signal is detected at the lhm pin ? turned off if a low signal is detected at the lhm pin 2.1.6 limp home mode the device enters limp home mode, if a microcontroller is detected, in the following cases: ? watchdog timeout in normal mode ?v cc1 under voltage (v cc1 < v cc1_th ) for more than 2 ms in normal mode ?v cc1 is below the v cc1_fail threshold for more than 4 ms during start-up ?v cc1 is below vcc1uv for more than 100 ms during start-up and v s is above v smin threshold ? thermal shutdown of v cc1 ? sdi stuck at 0 or 1 in limp home mode, all the control registers are set to their default values, except lh_sw (see section : control registers 3 ), which remains unchanged. the converter behaves according to the voltage level on the lhm pin: ? turned on if a high signal is detected at the lhm pin ? turned off if a low signal is detected at the lhm pin depending on the root cause, the action taken to quit the limp home mode (provided that the limp home condition has disappeared) is different. some of the recovery paths require the microcontroller to be supplied by external supply. a power on reset is always possible. docid025319 rev 1 11/69 L99LD01 functional description 68 figure 3. operating modes, main states 3 2 5 9 & & 6 w d u w x s 6 w d q g d o r q h 6 w d u w x s i d l o y f f r i i 1 r u p d o p r g h / l p s + r p h y f f r i i 6 : / l p s k r p h / l p s + r p h y f f r q 9 & & 8 9 9 6 9 6 p l q 9 & & 8 9 9 6 ! 9 6 p l q 9 & & ) d l o r u 9 & & 2 7 1 r x & 9 & & 2 . / k b v z r q / k b v z r i i : ' w u l j j h u ) d l o x u h q r w 2 7 5 & : ' w u l j j h u u g f r q v h f x w l y h : ' i d l o x u h 9 & & 2 7 5 & : ' w u l j j h u 5 & 5 h d g d q g & o h d u v w d w x v u h j l v w h u ) d l o x u h 6 ' , 6 w x f n w r + l j k r u / r z 2 5 z d w f k g r j w l p h r x w 2 5 9 f f 9 f f b w k i r u p r u h w k d q w \ s p v : ' w u l j j h u 2 5 9 & & 2 7 9 f f v w d \ v r i i ( " 1 ( $ ' 5 table 2. limp home mode: recovery paths transition root cause action to get back to normal mode response in the next spi command normal mode ? limp home v cc1 on wd timeout (1 st or 2 nd wd timeout) read and clear status1 and wd trigger fail safe bit = 0 wd_fail bit = 0 v cc1 < v cc1_th for more than 2ms fail safe bit = 0 vcc1_uv_to bit = 0 sdi stuck at 0 or 1 fail safe bit = 0 sdi_stuck@ = 0 functional description L99LD01 12/69 docid025319 rev 1 the following figure 4 , figure 5 (a), (b) and figure 6 (a) show the behavior of the device and nres during start-up in case of normal v s ramp up or in case of v cc1 failures (v cc1 fail or reset under voltage), both with microcontroller and standalone. figure 6 (b) and figure 7 show the behavior at v s ramp down fast and slow respectively. limp home v cc1 on ? limp home v cc1 off 3 consecutive wd timeouts (microcontroller is supplied by v cc1 ) power on reset or toggling of en pin fail safe bit = 0 wd_fail bit = 0 reset bit = 1 3 consecutive wd timeouts (microcontroller is supplied by another v reg ) read and clear status1 and wd trigger fail safe bit = 0 wd_fail bit = 0 start up ? limp home v cc1 off v cc1 < v cc1_fail during start up for more than 4 ms power on reset failsafe bit = 0 vcc1_sc bit = 0 reset bit = 1 v cc1 < v cc1_fail during start up for more than 4 ms (microcontroller supplied by another v reg ) read and clear status1 and wd trigger or toggling of en pin failsafe bit = 0 vcc1_sc bit = 0 vcc1_fail = 0 v cc1 < v cc1_th for more than 100 ms during start up and v s >v smin power on reset or toggling of en pin fail safe bit = 0 vcc1_sc bit = 0 reset bit = 1 v cc1 < v cc1_th for more than 100 ms during start up and v s >v smin (microcontroller supplied by another v reg ) read and clear status1 and wd trigger fail safe bit = 0 vcc1_sc bit = 0 any state except normal mode standalone ? limp home v cc1 off v cc1 over temperature read and clear status1 and wd trigger fail safe bit = 0 vcc1_ot bit = 0 normal mode ? sw limp home software limp home is activated reset lh_sw bit and wd trigger fail safe bit = 0 lh_sw_st = 0 table 2. limp home mode: recovery paths (continued) transition root cause action to get back to normal mode response in the next spi command docid025319 rev 1 13/69 L99LD01 functional description 68 figure 4. normal start up vs v s ramp up and v cc1 voltage dips note: normal start up with or without microcontroller. w 9 ) w w 5 5 9 v > 9 @ 9 f f > 9 @ 1 5 h v h w 9 3 2 5 9 & & b 7 + + l j k / r z 3 r z h u r q 5 h v h w w k u h v k r o g 9 & & ) $ , / w 6 + 7 9 $ w w 5 5 6 s h f l i l f d w l r q 3 d u d p h w h u v w 9 ) ) l o w h u w l p h i r u 9 f f ) d l o g h w h f w l r q w 5 5 9 f f 5 h v h w 7 l p h i l o w h u w l p h w 5 ' 5 h v h w g h o d \ w l p h w ) 6 9 f f u h v h w w l p h r x w i r u i d l o v d i h g h w h f w l r q w 6 + 7 9 $ i l o w h u w l p h e h i r u h g h w h f w l r q r i v k r u w f l u f x l w r q 9 f f d w w x u q r q 9 f f 9 f f ) $ , / w 6 + 7 9 % i l o w h u w l p h e h i r u h g h w h f w l r q r i v k r u w f l u f x l w r q 9 f f d w w x u q r q 9 f f ) $ , / 9 f f 9 & & b 7 + 9 & & b 7 + u h v h w l q w h u y h q w l r q w k u h v k r o g 9 6 0 , 1 p l q l p x p 9 v u h t x l u h g i r u u h d f k l q j 9 f f q r p l q d o y r o w d j h 9 & & b ) $ , / 9 f f i d l o g h w h f w l r q w k u h v k r o g 9 6 0 , 1 w 6 + 7 9 % w w ) 6 w w ) 6 9 f f b i d l o v w d w x v v h w w w 5 5 9 f f b x y b w r v w d w x v v h w $ 1 ' / l p s + r p h p r g h d f w l y d w h g l i ? & r q e r d u g p v w w 5 ' p v w w 5 ' p v w w 5 ' p v 6 w d u w x s / l p s + r p h l i ? & 6 w d q g e \ $ f w l y h p r g h 6 w d u w x s 6 w d q g e \ $ f w l y h p r g h ? & r q e r d u g 6 w d q g d o r q h ( " 1 ( $ ' 5 functional description L99LD01 14/69 docid025319 rev 1 figure 5. v cc1_fail or v cc1 reset under voltage (v s >v smin ) at start up 9 v > 9 @ 9 f f > 9 @ 1 5 h v h w 9 3 2 5 9 & & b 7 + + l j k / r z 3 r z h u r q 5 h v h w w k u h v k r o g 9 & & ) $ , / w w 6 + 7 9 $ 9 6 0 , 1 9 v > 9 @ 9 f f > 9 @ 1 5 h v h w 9 3 2 5 9 & & b 7 + + l j k / r z 3 r z h u r q 5 h v h w w k u h v k r o g 9 & & ) $ , / w w 6 + 7 9 $ 9 6 0 , 1 9 f f b i d l o v w d w x v v h w 9 f f b v f v w d w x v v h w 9 f f b r i i v w d w x v v h w / l p s + r p h p r g h d f w l y d w h g l i ? & r q e r d u g w w 6 + 7 9 % 9 f f b v f v w d w x v v h w 9 f f b r i i v w d w x v v h w / l p s + r p h p r g h d f w l y d w h g l i ? & r q e r d u g 6 w d u w x s / l p s + r p h 6 w d q g e \ 6 w d u w x s / l p s + r p h 6 w d q g e \ 6 w d u w x s $ f w l y h 0 r g h 6 w d q g e \ 6 w d u w x s $ f w l y h 0 r g h 6 w d q g e \ ? & r q e r d u g 6 w d q g d o r q h ? & r q e r d u g 6 w d q g d o r q h ( " 1 ( $ ' 5 b t u b s u v q 7 $ $ g b j m c 7 $ $ v o e f s s f t f u u i s f t i p m e e v s j o h t u b s u v q 7 4 7 4 . * / b c docid025319 rev 1 15/69 L99LD01 functional description 68 figure 6. v cc1 reset under voltage at start up (v s < v smin ) and fast v s ramp down ( " 1 ( $ ' 5 9 v > 9 @ 9 f f > 9 @ 1 5 h v h w 9 3 2 5 9 & & b 7 + + l j k / r z 3 r z h u r q 5 h v h w w k u h v k r o g 9 & & ) $ , / w w 6 + 7 9 $ 9 6 0 , 1 w w 6 + 7 9 % a p v 9 f f b v f v w d w x v v h w 9 f f b r i i v w d w x v v h w 9 v b x y v w d w x v v h w 1 r / l p s + r p h p r g h d f w l y d w h g 9 v 9 v p l q 9 v 9 v p l q 6 w d u w x s 6 w d u w x s 9 f f r i i 6 w d q g e \ ? & r q e r d u g 6 w d q g d o r q h 6 w d u w x s $ f w l y h 0 r g h 6 w d q g e \ 9 v > 9 @ 1 5 h v h w 9 3 2 5 9 & & b 7 + + l j k / r z 9 & & ) $ , / 9 6 0 , 1 $ f w l y h 0 r g h 9 v b x y v w d w x v v h w w w 5 5 6 w d q g e \ $ f w l y h 0 r g h 6 w d q g e \ ? & r q e r d u g 6 w d q g d o r q h b 7 $ $ @ 6 7 e v s j o h t u b s u v q c 7 4 7 4 . * / ' b t u 7 4 s b n q e p x o b c functional description L99LD01 16/69 docid025319 rev 1 figure 7. slow vs ramp down 2.2 protections and functions 2.2.1 led current adjust and temperature control the led current can be adjusted within a range of 66.7 %, with respect to the default value set by the led current sense resistor, via the spi input, so allowing the end of line calibration. the led chain temperature measurement is achieved by means of an external ntc resistor connected between the ntc pin and gnd. the ntc resistor is supplied through a resistor connected to the 5 v internal regulator output. as soon as the voltage on the ntc resistor becomes lower than the internal threshold, v ntc_th , (due to an overtemperature in the led chain) an internal circuitry is activated and the internal led current reference voltage decreases proportionally, so that the led current is progressively p v 9 v > 9 @ 1 5 h v h w 9 3 2 5 9 & & b 7 + + l j k / r z 9 & & ) $ , / 9 6 0 , 1 1 r u p d o 0 r g h 9 v b x y v w d w x v v h w w w 5 5 6 w d q g e \ 1 r u p d o 0 r g h ? & r q e r d u g 6 w d q g d o r q h w w 9 6 0 9 f f > 9 @ 6 w d q g e \ w w ) 6 / l p s + r p h 9 f f b x y b w r v w d w x v u h j l v w h u ( " 1 ( $ ' 5 docid025319 rev 1 17/69 L99LD01 functional description 68 reduced (maximum 50 % of the nominal led current), not allowing the led temperature to increase over the programmed limit. thermal limit intervention is reported by properly setting a bit inside the internal status register. 2.2.2 slope compensation slope compensation is needed to ensure the stability of the control loop with all possible values of duty cycle (0 < d < 1) especially for duty cycle greater than 0.5. the recommended slope s add of the additional ramp is proportional to the inductor current slope during the turn off phase, that is: where s add is the additional slope introduced by the circuit, is the off-time inductor slope and s l is also given by the formula: being g la the gain of the linear amplifier (see chapter 5: electrical characteristics for g la parameter values) and r shunt is the resistor across pin i sp and i sn (see chapter 7: application circuits ). the simplified internal circuit structure for the slope compensation is shown in figure 8 . the additional slope is obtained from the internal oscillator ramp voltage. a fraction of the oscillator voltage ramp is added to the output voltage of the sensing amplifier, which is proportional to the sense resistor voltage drop, and therefore, to the current flowing through power mosfet m1. the added ramp voltage is where d t on t ----------- = s add s l ? = s l di l dt ------- - off = 0.5 1 << ? () ?? l -------------------------------------------------------------------------------- = v add ir slope ? = functional description L99LD01 18/69 docid025319 rev 1 and r slope and r t are defined in the figure 8 , together with their typical values. therefore, will result: and consequently: where t is the period of the converter oscillator. the additional compensating current slope can be simply adjusted by properly setting the value of the external resistor r9 (and consequently r t ). figure 8. internal structure of the slope compensation circuit 2.2.3 led chain overvoltage detection via the external resistor divider (r5, r6) it is possible to detect led overvoltage events, by programming a threshold for the maximum drop voltage of the led chain for a specific led board (see section 2.2.12 for details). in case boost or fly back topology is used, the l mode pin must be connected to gnd. in this case the voltage at pin v led will be referred to ground. instead, if buck boost topology is used, the l mode pin must be connected to 5 v or left open. an internal pull up current source keep this pin high, and in this case, the voltage applied by the resistor divider r5/r6 at pin v led will be referred to the battery voltage applied at pin v s . if a valid overvoltage event occurs, which is detected if the led drop voltage reaches a value v led ov_th1, the device is switched off immediately forcing the i2 v osc r t --------------- - ? = v add 2v osc r slope r t ---------------------- - ?? = s add v add t --------------- 2v osc r slope ?? r t t ? --------------------------------------------------- == 6 & 9 9 2 6 & . . 5 6 & 5 2 7 $ 3 : 0 & r p s / $ p s , 9 2 6 & 5 7 5 6 / 2 3 ( . 5 & & 2 0 3 5 ( 6 , 6 1 , 6 ( 1 6 ( , 6 3 , 6 ( 1 6 ( 5 7 5 6 & 5 6 & 5 6 & p l q . 2 + 0 , ( " 1 ( $ ' 5 docid025319 rev 1 19/69 L99LD01 functional description 68 pins g1 and g2 to zero voltage and the event is registered in the status register of the spi interface and read by the micro. in case of led overvoltage, immediately after stopping the device, an internal resistor is applied between pin i sense+ and gnd trough the switch ?c_disch? (see figure 1 ), in order to discharge capacitors c1 and c4, avoiding led flashing when the converter restarts. any led_ov event will be written in the gsb (global status byte) bit 7 and also in the sr1 (status register 1) bit 18. 2.2.4 battery overvoltage shutdown in case supply voltage applied to the v s pin rises above a maximum voltage threshold, sensed by a resistor divider attached at pin inp_ov, the converter is switched off immediately, forcing outputs pin g1 and g2, to zero voltage. this prevents a led over current in case of load-dump. if, following the input overvoltage event, the battery voltage decreases under a second threshold, lower than the former, the converter starts again. 2.2.5 regulators thermal shut down both voltage regulators inside the chip are provided with over temperature detection circuits. if v r1 reaches its maximum temperature, v r1 will be switched off. after that, the behavior of the device depends on the application (see section 2.2.1: led current adjust and temperature control ). if instead, is v r2 to reach its maximum temperature (typ 175 c), then the device will be completely switched off (v cc1 and v cc2 =0). only the internal temperature monitoring of v cc2 remains alive and when the temperature falls down under a second lower temperature threshold (150 c typ.), the device tries to restart again. 2.2.6 reset the nres pin (active low), generates a reset signal for the microcontroller. an external pull up resistor (typ. 100 k) maintain normally high the voltage at pin nres (see figure 32 ). following a power up condition, the nres pin is forced low while the voltage provided by regulator 1 (v cc1 ) is below an internal fixed threshold v cc1_th of typ 4.5 v. after v cc1 has reached the above mentioned internal threshold, nres voltage is kept low for a fixed default time of 2 ms; after that, the nres pin will be released reaching the normal high state. however, this time can be externally extended by an additional capacitance connected between nres and gnd (see c6 in the application circuits), which is charged by the external pull-up. depending on the reset-input-threshold of the p (u tr ), the required capacitance for a typical t rd can be calculated as follows: r pu is the pull up resistor (value in ohm) c6 t ? rd r pu lg 1 u tr v cc1 ? ? () ? () ? = functional description L99LD01 20/69 docid025319 rev 1 in case v cc1 voltage drops below the internal threshold during the normal functioning, or when the device is put in standby, the nres pin is forced to low, but after a time interval t rr has expired and kept low until the v cc1 has gone back again to the internal threshold (see figure 4 for more details). 2.2.7 watchdog in case the application uses a microcontroller, during the device power-up a reset pulse is generated periodically every 200 ms (default) for 2.0 ms waiting for microcontroller acknowledgment. timeout window is selectable by spi (100 ms or 200 ms) and the reset time could be extended by the external capacitor c6. ? timeout wd is refreshed by bit toggling. ? after the 1 st wd timeout, a reset pulse is generated and the device enters in limp home mode. after the second wd timeout, another reset pulse cycle is generated, waiting for microcontroller response. ? after 3 consecutive reset cycles without wd refresh, which means that microcontroller is not responding, the voltage regulator, v cc1 , is turned off and the device keeps working in ?limp home mode? (see figure 33 ). safety critical functions like low beam application require the led driver to be turned on if the microcontroller fails, while in case of high beam application, it is required the driver to be switched off in case of microcontroller failure. as a consequence, the device operates according to the state of lhm pin which is enabled during the recognition of the microcontroller failure. in particular, if lhm pin is kept low the device will be always off. if instead, lhm pin is high or left open, the device will be switched permanently on, regardless of the status of pwm_l pin.if the application doesn?t use a microcontroller (stand alone operation), the start-up wd control must to be deactivated. this can be done by connecting nres pin to the battery supply voltage v s . in such a case the driver will operate in normal mode as above mentioned (see stand alone operation). 2.2.8 standby and wake up by enable pin a low consumption mode is required in case of applications directly connected to the battery. the device enters in standby mode, that is the default operating modes because of an internal pull down, in case of low level signal at the enable pin and it wakes up in case of high level signal.during standby mode, v cc1 and v cc2 are switched off. figure 9 and figure 10 show two possible application schematics in case of direct connection to the battery. in case of figure 9 the microcontroller of the application goes in standby when the microcontroller sets the lin transceiver in standby mode: nslp = low inh goes low the drl driver goes in standby. the application is waken up from the standby when a wake up source is detected by the lin transceiver. that means inh goes high and so enable, then the drl driver restarts and consequently v cc1 is activated and supplies the microcontroller. in case of figure 10 , a power management device is present, which supplies the microcontroller. normally the inverted fso signal coming from the power management device is high. this output is inverted by an external logic and applied to one of the two input or diodes and therefore, at the input of the or the voltage is normally at logical zero. docid025319 rev 1 21/69 L99LD01 functional description 68 so in this case the led driver goes: ? in stand-by mode with a low level on enable pin operated by the microcontroller ? in normal mode with a high level on enable pin operated by the microcontroller the inverted fso signal, coming from the power management device ensures, putting trough the inverter and the external or diode enable pin high, that the led driver correctly restarts even if the microcontroller fails. figure 9. operation with a standalone lin and enable figure 10. operation with pm device and enable (fso active low) 1. an inverter network is required. 2.2.9 frequency setting and dither effect the internal main converter oscillator structure is reported in figure 11 . 9 % $ 7 7 / ( ' 0 r g x o h ? & / , 1 9 1 6 / 3 , 1 + ' 5 / ' u l y h u ( 1 $ % / ( ( " 1 ( $ ' 5 ( " 1 ( $ ' 5 9 % $ 7 7 / ( ' 0 r g x o h ? & / , 1 3 r z h u p d q d j h p h q w 9 ) 6 2 ' 5 / ' u l y h u ( 1 $ % / ( ) 6 2 functional description L99LD01 22/69 docid025319 rev 1 the external resistor applied between pin r sf and ground is setting the converter working frequency. the voltage applied on pin r sf is the internal reference reported by the source follower structure which is a constant voltage of 1.21 v. the converter frequency is directly related to the current flowing through the r sf pin. figure 12 reports the behavior of frequency converter as function of the external resistor r sf and i rsf as function of converter frequency. as above mentioned the converter oscillator spread parameters (dither effect) are adjustable via spi. dither effect is disabled by default during standalone operation, but it is possible enabling it simply connecting the sdi pin to 5 v voltage. figure 11. internal structure of main converter oscillator , f . , 5 6 ) 5 6 ) , 5 6 ) 5 6 ) 2 v f l o o d w r u 9 , 5 6 ) ( " 1 ( $ ' 5 docid025319 rev 1 23/69 L99LD01 functional description 68 figure 12. converter frequency range vs r sf and i rsf vs frequency 2.2.10 start up led overvoltage management the following diagram shows the purpose of delay time windows ?t dstart ? and ?t enrecov ?. the first delay window t dstart has been thought to ensure an initial time period for charging the external buffer capacitor of the charge pump c9. when v s is below v smin , the led overvoltage recovery bit is set. during this time interval, triggered as soon as the battery voltage v s overcomes v smin threshold, the converter remain in a stop condition, independently from pwm_l. when the t dstart is elapsed (typ. 5 ms), the converter is released and behaves according to the pwm_l signal provided, that no failure occurs. if no led overvoltage comes during the 2 nd time interval t enrecov , led ov recovery bit is reset. ( " 1 ( $ ' 5 , 5 6 ) y v ) u h t x h q f \ , 5 6 ) ) 5 ( 4 ) 5 ( 4 > . k ] @ , 5 6 ) > x $ @ ) u h t x h q f \ y v 5 6 ) 5 6 ) > . @ ) 5 ( 4 > . k ] @ functional description L99LD01 24/69 docid025319 rev 1 if a led overvoltage failure occurs afterwards, the failure will be latched and the converter is stopped until a read and clear of the status register 1. note that during t dstart , the converter is stopped to enable the buffer capacitor c9 to charge at a sufficient voltage to correctly drive the mosfet m2. this delay prevents the converter to turn on, while m2 stays off, avoiding a led overvoltage event. if the application uses a big capacitor (a) , it is recommended to keep the pwm_l signal low after a power on reset or after a v s under voltage, until c9 is totally charged, to avoid a led overvoltage. figure 13 shows the device behavior in case of no led overvoltage failure, after t dstart . if c9, after t dstart time, should be not enough charged to allow correct driving operation, a possible led overvoltage will appear when, the converter will be released. figure 14 shows what happens in this case. after t dstart , the converter is released while the c9 capacitor is only partially charged. consequently, v led increases up to led ov_th1 and a led overvoltage event is detected during the t enrecov phase. the led_ov_rec bit is not reset at the end of the t enrecov phase due to the led overvoltage event. the discharge path is activated until v led crosses led ov_th2. then, the led_ov_rec bit is reset, the converter is released, and the buffer capacitor c9 is now fully charged, enabling the dimming mosfet m2 to turn on. figure 15 shows the case of led_ov_rec bit during a start up with a rising edge on pwm_l = high after the expiration of t dstart . in this case, the t enrecov phase starts only when the pwm_l signal goes high. figure 16 shows the case of led overvoltage event, which could appear during normal functioning. the led overvoltage status bit is set (latched) and the discharge path is activated until v led crosses led ov_th2. the converter is stopped, independently from pwm_l, until a read and clear command of the status register 1 (led_ov_rec bit is reset). if a led overvoltage failure event occurs during v s overvoltage, (battery ov), the discharge path for the output capacitor is inhibited and the led overvoltage status bit is not set. when the v s overvoltage event disappears, (v s crosses v s ov_th2), the led overvoltage status bit is set (latched) and the discharge path is activated until v led crosses led ov_th2. the converter is stopped, independently from pwm_l, until the led ov status bit is cleared (read and clear of the status register 1). figure 17 shows such a case. finally figure 18 shows how will be managed the led_ov_rec bit in case signal pwm_l has a low on-time. in this case the led_ov_rec bit is reset when the cumulated running time of t enrecov exceeds typ. 5 ms. this feature enables a single recovery of a led overvoltage event, due to a too fast regulation loop (set by the resistor and capacitor connected to rccomp pin), even in pwm operation with low on-time. however, a proper choice of rc network values, avoiding fast transients on the led string voltage, when the converter is switched on, it is carefully recommended a. more than 22 nf docid025319 rev 1 25/69 L99LD01 functional description 68 figure 13. correct start up with no led overvoltage failure figure 14. led overvoltage after t dstart & r q y h u w h u 9 v 9 v b p l q 3 : 0 b / 7 l p h u w ' 6 w d u w a p v w ( q 5 h f r y a p v 2 ) ) 2 1 / ( ' r y u h f r y e l w 3 2 5 6 l q j o h / ( ' r y u h f r y h u \ h q d e o h g 5 h f g l v d e o h g ( " 1 ( $ ' 5 w ( q 5 h f r y a p v & r q y h u w h u 9 v 9 v b p l q 3 : 0 b / 7 l p h u w ' 6 w d u w a p v 2 ) ) 2 ) ) / ( ' r y u h f r y e l w 3 2 5 / ( ' 2 y b w k / ( ' 2 y b w k 2 x w s x w f d s ' l v f k d u j h / ( ' r y h u y r o w d j h g x u l q j w k h w ( q 5 h f r y s k d v h 7 k h h q g r i w k h w ( q 5 h f r y s k d v h l v l j q r u h g e h f d x v h g r i w k h / ( ' r y h y h q w w k h / ( ' r y u h f r y h u \ e l w l v q r w u h v h w 2 1 ( " 1 ( $ ' 5 functional description L99LD01 26/69 docid025319 rev 1 figure 15. device behavior in case the low to high transition of pwm_l signal happens after t dstart expiration figure 16. led overvoltage event not caused by a vs overvoltage event & r q y h u w h u 9 v 9 v b p l q 3 : 0 b / 7 l p h u : d l w l q j i r u 3 : 0 b / u l v l q j 2 ) ) 2 1 / ( ' 2 y u h f r y e l w w ( q 5 h f r y a p v w ' 6 w d u w a p v 6 l q j o h / ( ' r y u h f r y h u \ h q d e o h g / ( ' r y u h f r y h u \ g l v d e o h g 3 2 5 ( " 1 ( $ ' 5 & r q y h u w h u 2 1 2 x w s x w f d s ' l v f k d u j h 2 ) ) 2 ) ) 2 1 2 ) ) 9 / ( ' / ( ' 2 y b w k / ( ' 2 y b w k / ( ' r y v w d w x v e l w 5 h d g d q g & o h d u 6 w d w x v 5 h j 9 v 9 v 2 y b w k 9 v p l q 2 1 ( " 1 ( $ ' 5 docid025319 rev 1 27/69 L99LD01 functional description 68 figure 17. led overvoltage detection due to a possible battery vs overvoltage figure 18. behavior of led overvoltage recovery bit with low on-time of pwm_l 2.2.11 programming the over/under voltage threshold the voltage across the led string is continuously sensed by the external resistor divider r5/r6 and reported inside the chip trough the apposite pin v led. considering negligible the voltage drop due to the sense resistor and the v ds of external mosfet m2 respect to the led 9 v 9 v 2 y b w k 9 v 2 y b w k & r q y h u w h u 2 1 ' l v f k d u j h 2 ) ) 2 ) ) 2 1 2 ) ) 9 / ( ' / ( ' 2 y b w k / ( ' r y v w d w x v e l w 5 h d g d q g & o h d u 6 w d w x v 5 h j / ( ' 2 y b w k ( " 1 ( $ ' 5 & r q y h u w h u 9 v 9 v b p l q 3 : 0 b / 7 l p h u w ' 6 w d u w a p v / ( ' r y u h f r y e l w 3 2 5 ( [ s l u d w l r q r i w ( q 5 h f r y f x p x o d w h g u x q q l q j w l p h a p v : d l w 3 : 0 / 5 l v l q j w ( q 5 h f r y 5 x q q l q j w ( q 5 h f r y + d o w w ( q 5 h f r y 5 x q q l q j w ( q 5 h f r y + d o w w ( q 5 h f r y 5 x q q l q j w ( q 5 h f r y + d o w w ( q 5 h f r y 5 x q q l q j 2 1 2 ) ) ( [ s l u d w l r q r i w ' v w d u w 6 l q j o h / ( ' r y u h f r y h u \ h q d e o h g 5 h f r y h u \ g l v d e o h g & r q y h u w h u 9 v 9 v b p l q 3 : 0 b / 7 l p h u w ' 6 w d u w a p v / ( ' r y u h f r y e l w 3 2 5 ( [ s l u d w l r q r i w ( q 5 h f r y f x p x o d w h g u x q q l q j w l p h a p v : d l w 3 : 0 / 5 l v l q j w ( q 5 h f r y 5 x q q l q j w ( q 5 h f r y + d o w w ( q 5 h f r y 5 x q q l q j w ( q 5 h f r y + d o w w ( q 5 h f r y 5 x q q l q j w ( q 5 h f r y + d o w w ( q 5 h f r y 5 x q q l q j 2 1 2 ) ) ( [ s l u d w l r q r i w ' v w d u w 6 l q j o h / ( ' r y u h f r y h u \ h q d e o h g 5 h f r y h u \ g l v d e o h g ( " 1 ( $ ' 5 functional description L99LD01 28/69 docid025319 rev 1 voltage string, according to the equation reported below, the led overvoltage thresholds are given by the following formulas: v led_ov =ov_th1 / k l ; being k l =r6 / (r5+r6); ov_th1 is the reference for the ov internal comparator. typical value for ov_th1 is 3.5 v. led ov event makes the converter and also mosfet m2 immediately switched off, in order to prevent any damage to the led string or to the driver. furthermore, following an ov event, the led_ov status register is set and an internal load is applied between i sense+ pin and ground in order to fast discharge the voltage across capacitor c4. in the boost topology application, if a short circuit between the source of external mosfet m2 and gnd occurs, an uncontrolled current could flow. in order to avoid this situation, a maximum led current protection has been inserted, which continuously monitors the voltage across the sense resistor r sense . if this voltage reaches a value in excess of an internal fixed threshold of (see table 24 - led over current protection threshold parameter), the status bit led_oc (led over current) is set and the converter and also mosfet m2 will be immediately switched off. following a stop of the converter due to an ov event, the device can not be restarted before of c4 discharge (v led is below ov_th2). after an ov event, the converter could restart if a read and clear command of the led_ov status bit is done. ta ble 3 summarizes the suggested value of k l resistor ratio, supposing to have a led_ov event, when the voltage across led string, reaches a value in excess of 50 % of its nominal value. figure 19. led chain overvoltage thresholds settings. an example for boost and fly back converters 9 % $ 7 7 5 9 / ( ' 6 7 5 , 1 * 5 0 1 2 9 b & 2 0 3 2 9 b 7 + 9 / ( ' 2 9 0 5 6 ( 1 6 ( & 9 / ( ' . / 9 / ( ' 6 7 5 , 1 * 9 / ( ' b 2 9 2 9 b 7 + . / . / 5 5 5 ( " 1 ( $ ' 5 docid025319 rev 1 29/69 L99LD01 functional description 68 2.2.12 input overvoltage programming supply overvoltage is programmed by the external partition ratio k i =r3/r4 according to the figure 20 input overvoltage thresholds depend on the internal reference voltages v ovth1 and v ovth2 (being v ovth2 < v ovth1 ) typical values of these internally generated references are 3.5 v and 3 v. when the battery voltage reaches a value in excess to v s_th1 the converter is immediately stopped. when the battery voltage, going down, reaches a value just lower to v s_th2 , the converter restarts again. figure 20. input overvoltage programming table 3. suggested k l value and overvoltage thresholds n number of led k l led chain nominal drop n*v f [v] overvoltage v led_ov [v] 1 (1) 0.583 4 6 2 (1) 0.292 8 12 3 (1) 0.194 12 18 4 (1) 0.146 16 24 5 0.117 20 30 6 0.097 24 36 7 0.083 28 42 8 0.073 32 48 9 0.065 36 54 (2) 10 0.0583 40 60 (2) 1. not applicable on boost converter topology, since the chain led drop must be always larger as the maximum battery voltage. 2. theoretical value; effective value will be clamped to 52 v (typ) by the ov protection. 9 6 b 7 + 5 5 9 2 9 7 + 9 6 b 7 + 5 5 9 2 9 7 + , 1 3 b 2 9 9 2 9 7 + & 5 5 9 % $ 7 7 9 6 ( " 1 ( $ ' 5 functional description L99LD01 30/69 docid025319 rev 1 as an example, if we want v s_th1 = 20 v, according to the formula of figure 20 , r3/r4 will result equal to 4.7 and consequently the deactivation threshold v s_th2 will result ~ 17 v. (b) b. notice that the deactivation threshold must be always greater than the maximum allowed battery value in normal conditions. docid025319 rev 1 31/69 L99LD01 spi functional description 68 3 spi functional description 3.1 serial peripheral interface (st spi standard) the spi communication is based on a standard st-spi 24-bit interface, using csn, sdi, sdo and sck signal lines. input data are shifted into sdi, msb first while output data are shifted out on sdo, msb first. during active mode, the spi: ? triggers the watchdog ? controls the modes and status of all internal modules (incl. input and output drivers) ? provides driver output diagnostic ? provides device diagnostic (incl. over temperature warning, device operation status) note: during standby modes, the spi is generally deactivated. the spi can be driven by a microcontroller with its spi peripheral running in following mode: figure 21. clock polarity and clock phase according to the standard, a generic input bit is sampled by the low to high transition of the clock clk and a generic output bit changes synchronously to the high to low transition of clk. this device is not limited to micro controller through a built-in spi. only three cmos- compatible output pins and one input pin will be needed to communicate with the device. a fault condition can be detected by setting csn low. if csn = 0, the do pin will reflect the global error flag (fault condition) of the device (see figure 22 ). this operation does not cause a communication error bit in the global status byte to be set. & 3 2 / & 3 + $ & 6 1 6 & . 6 ' , 6 ' 2 0 6 % / 6 % 0 6 % / 6 % + , + , * $ 3 * & ) 7 spi functional description L99LD01 32/69 docid025319 rev 1 figure 22. spi global error information output 3.2 signal description ? serial clock (sck): this input signal provides the timing of the serial interface. data present at serial data input (sdi) is latched on the rising edge of serial clock (sck). data on serial data out (sdo) is shifted out at the falling edge of serial clock (sck). ? serial data input (sdi): this input is used to transfer data serially into the device. it receives the data to be written. values are latched on the rising edge of serial clock (sck). ? serial data output (sdo): this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (sck). sdo also reflects the status of the docid025319 rev 1 33/69 L99LD01 spi functional description 68 at the beginning of each communication the master device read the contents of the spi functional description L99LD01 34/69 docid025319 rev 1 3.3.3 operating code definition the spi interface features four different addressing modes which are listed in ta ble 10 . the docid025319 rev 1 35/69 L99LD01 spi functional description 68 during the same sequence outgoing data are shifted out msb first on the falling edge of the csn pin and subsequent bits on the falling edge of the serial clock (sck). the first byte corresponds to the global status byte and the second to the previous content of the addressed register. figure 23. spi write operation read mode the read mode of the device allows to read and to check the state of any register. incoming data are sampled on the rising edge of the serial clock (sck), msb first. outgoing data are shifted out msb first on the falling edge of the csn pin and others on the falling edge of the serial clock (sck). the first byte corresponds to the global status byte and the second to the content of the addressed register. in case of a read mode on an unused address, the ?global status/error? byte on the sdo pin is following by 00h byte. in order to avoid inconsistency between the global status byte and the status register, the status register contents are frozen during spi communication. figure 24. spi read operation read and clear status command the read and clear status operation is used to clear the content of the addressed status register (see section : status registers 1 ). a read and clear status operation with address csn sdo sdi 0msb msb msb lsb lsb lsb lsb command byte global status byte (8 bit) data (previous content of register) data (8 bit) 0 address msb csn sdo sdi msb msb msb lsb lsb lsb command byte global status byte (8 bit) data (8 bit) don?t care (8 bit) 0lsb 1 address msb spi functional description L99LD01 36/69 docid025319 rev 1 3fh clears all status registers simultaneously and reads back the configuration register (globctr). incoming data are sampled on the rising edge of the serial clock (sck), msb first. the command byte allows to determine which register content is read then erased while the data byte is ?don?t care?. outgoing data are shifted out msb first on the falling edge of the csn pin and others on the falling edge of the serial clock (sck). the first byte corresponds to the global status byte and the second to the content of the addressed register. in order to avoid inconsistency between the global status byte and the status register, the status register contents are frozen during spi communication. figure 25. spi read and clear operation read device information specific information can be read but not modified during this mode. incoming data are sampled on the rising edge of the serial clock (sck), msb first. the command byte allows to determine which information is read while the data byte is ?don?t care?. outgoing data are shifted out msb first on the falling edge of the csn pin and others on the falling edge of the serial clock (sck). the first byte corresponds to the global status byte and the second to the content of the addressed register. csn sdo sdi msb msb msb lsb lsb lsb command byte global status byte (8 bit) data (8 bit) don?t care (8 bit) 1lsb 0 address msb docid025319 rev 1 37/69 L99LD01 spi functional description 68 figure 26. spi read device information 3.4 address mapping t csn sdo sdi msb msb msb lsb lsb lsb command byte global status byte (8 bit) data (8 bit) don?t care (8 bit) 1lsb 1 address msb table 10. ram memory map address name access content 00h reserved read/write reserved 01h control register 1 read/write mux settings, wd period and retrigger 02h control register 2 read/write spread spectrum settings, max input current and led current settings 03h control register 3 read/write sw limp home, ota/driver and converter delay control 04h status register 1 read detailed status information 05h status register 2 read wd status, operation mode and lmode error 3e trimming and test read trimming bus and test mode select 3f configuration reg. read/write wd retrigger bit table 11. rom memory map address name access content 00h id header read only 4300h (assp st_spi) 01h version read only 0100h 02h product code 1 read only 3100h (dec. 49) 03h product code 2 read only 5100h (ascii ?q?) 3eh spi frame id read only 4200h (watchdog available, 24 bit st-spi) spi functional description L99LD01 38/69 docid025319 rev 1 3.5 control registers (ram) control registers 1 address: 0x01h type: r/w reset: 0000 0000 0000 1110b 1514131211109876543210 reserved mux[[1:0] mux_en en_ntc wd_period wd_trig bit [6:15] reserved bit [5:4] mux[1:0]: 00 (default): the signal on the pwm pin is reflected on mout pin 01: the signal on the v led is reflected on mout pin 10: the signal on ntc is selected 11: the signal on lmode pin is selected bit [3] mux_en: 0: the mout pin is inactive (tristate) 1: the mout pin is active (default) bit [2] en_ntc: when set, the current fold back feature enabled in case of led overtemperature conditions. this bit is ignored in case of any limp mode and the led temperature monitoring is activated (the ntc control is internal) bit [1] wd_period: 0: wd timeout = 100 ms 1: wd timeout = 200 ms (default) bit [0] wd_trig: this bit must be toggled within the wd period to refresh the wd docid025319 rev 1 39/69 L99LD01 spi functional description 68 control registers 2 address: 0x02h type: r/w reset: 0101 1110 0001 1111b 1514131211109876543210 fdev[2:0] fmod[1:0] dith_en led_curr[4:0] max_curr[4:0] bit [15:13] fdev[2:0]: frequency deviation of the internal oscillator (see table 12 ) bit [12:11] fmod[1:0]: frequency modulation of the internal oscillator (see table 13 ) bit [10] dith_en: enable or disable random dither effect. if this bit is set dithering is enabled; if the bit is reset, the dithering is disabled bit [9:5] led_curr[4:0]: these bits set the led current. the led current is given by: 0.05 + (0.2 * led_curr[4:0]d) / 31) / (r sense ) [a] (typ) where led_curr[4:0]d = decimal value of led_curr[4:0] bit [4:0] max_curr[4:0]: these bits set the maximum input current. the internal current limiter voltage threshold is: 1 + (2.5 * max_curr[4:0]d) / 31 in [v] (typ) considering the gain of the amplifier of 10, the current limitation is: (1 + 2.5 * max_curr[4:0]d / 31) / (10 r shunt ) (typ); where max _curr[4:0]d = decimal value of max_curr[4:0] table 12. internal oscillator frequency deviation settings fdev[2] fdev[1] fdev[0] frequency deviation 000 0% 001 5% 010 10% 011 15% 100 20% 101 25% 110 30% table 13. internal oscillato r frequency modulation settings fmod[1] fmod[0] frequency modulation 0 0 1.95 khz 01 3.9khz 10 7.8khz 1 1 15.6 khz spi functional description L99LD01 40/69 docid025319 rev 1 control registers 3 address: 0x03h type: r/w reset: 0000 1000 0000 0000b 1514131211109876543210 reserved lh_sw ctrl_ota[3:0] ctrl_drv[3:0] bit [15:13] reserved bit [12] lh_sw: the device goes in limp home mode without wd supervision (v cc1 stays on) when the bit is set bit [11:8] ctrl_ota[3:0]: these bits set the delay between a rising edge of the pwm_l signal and a connection of the output of the operation transconductance amplifier. the delay is given by ctrl_ota[3:0]d * 3.3 s (typ.) where ctrl_ota[3:0]d is the decimal value of ctrl_ota[3:0] the default of these bits are loaded from the corresponding control bus bit [7:4] ctrl_drv[3:0]: these bits set the delay between a rising edge of the pwm_l signal and the activation of the converter the delay is given by: ctrl_drv[3:0]d * 1.67 s (typ.) where ctrl_drv[3:0]d is the decimal value of ctrl_drv[3:0] the default of these bits are loaded from the corresponding control bus bit [3:0] ctrl_sw[3]: these bits set the delay between the falling edge of the pwm_l signal and the turn off of the dimming mosfet m2. the delay is given by: ctrl_sw[3:0]d * 1.67 s (typ.) where ctrl_sw[3:0]d is the decimal value of ctrl_sw[3:0] the default of these bits are loaded from the corresponding control bus. docid025319 rev 1 41/69 L99LD01 spi functional description 68 3.6 status registers status registers 1 address: 0x04h type: r/c 1514131211109876543210 reserved lmode_err vs_ov vs_uv led_temp_war led_oc led_ov vcc1_off vcc1_fail vcc1_uv_to vcc1_ot vcc1_sc sdi_stuck@ wd_fail ? r (1) r r (1) r/c (2) r r/c (2) 1. ?read only?, real time bit. 2. these bits are latched until a ?read and clear? access. bit [15:13] reserved bit [12] lmode_err: this bit is set if a mismatch between the signal on lmode pin and vled pin is detected. bit [11] vs_ov: is set if an overvoltage event at the supply line is detected bit [10] vs_uv: is set if an under voltage event at the supply line is detected bit [9] led_temp_warn: temperature warning for the led bit [8] led_oc: is set if an over current event across the led chain is detected bit [7] led_ov: is set if an overvoltage event across the led chain is detected bit [6] vcc1_off: when set, this bit indicated that v cc1 is off bit [5] vcc1_fail indicates that: v cc1 is below v cc1_fail threshold for typ. 2 s in active mode v cc1 is below v cc1_fail threshold for more than 4 ms typ. during start up bit [4] vcc1_uv_to: this bit is set in active mode if v cc1 is below the reset threshold for more than typ. 2 ms bit [3] vcc1_ot: set if an overtemperature condition has been detected on v cc1 bit [2] vcc1_sc: indicates a short circuit on v cc1 . this bit is set if v cc1 stays below the v cc1_fail threshold 4 ms (typ.) after the power on reset or below the reset threshold 100 ms after the por (power on reset) bit [1] sdi_stuck@ bit [0] wd_fail spi functional description L99LD01 42/69 docid025319 rev 1 status registers 2 address: 0x05h type: r 1514131211109876543210 reserved led_ov_rec ext_vcc pwm_l standalone lhm lh_sw_st wd_status[2:0] ?r r (1) r r (1) r r (2) 1. ?read only?, real time bit. 2. ?read only? bit. these bits are cleared by a wd re-trigger. bit [15:9] reserved bit [8] led_ov_rec once this bit is set, the device will make a single trial to recover from an led overvoltage. bit [7] ext_vcc: this bit reflects the signal on the ext_vcc pin, bit [6] pwm_l: this bit reflects the signal on the pwm_l pin bit [5] standalone: this bit is set if the device operates in standalone mode, without microcontroller bit [4] lhm: reflects the level at lhm pin bit [3] lh_sw_st: is set if the software limp home mode is activated bit [2:0] wd_status[2:0]: these bits indicate the status of the watchdog timer (see table 14 and see figure 27 ) table 14. watchdog timer status wd_status[1] wd_status[1] wd_status[0] wd timer status 000 [0?25%[ 001 [25% ? 50%[ 011 [50% ? 75%[ 111 [75% ? 100%[ docid025319 rev 1 43/69 L99LD01 spi functional description 68 figure 27. principle of the wd_status bits trimming and test register address: 0x3eh type: r/w reset: 0000 0000 0000 0000b configuration register address: 0x3fh type: r/w reset: 0000 0000 0000 0000b 7 l p h r x w : ' 7 l p h u : ' 5 h i u h v k : ' 5 h i u h v k : ' 6 w d w x v > @ ( " 1 ( $ ' 5 1514131211109876543210 tm[5:0] trim_bus[9:0] r/w r bit [15:10] tm[5:0]: test mode selection (refer to the uq49 test controller) bit [9:0] trim_bus[9:0]: copy of the data stored in the trimming fuse cells 151413121110987654321 0 reserved wd_trig ?r/w bit [15:1] reserved bit [0] wd_trig: this bit must be toggled within the wd period to refresh the wd. note that this bit is copied in the control register 1, bit 0 electrical specifications L99LD01 44/69 docid025319 rev 1 4 electrical specifications figure 28. voltage and current conventions 4.1 absolute maximum ratings 9 6 & . , & & , 1 7 & , ( ; 7 9 & & , 6 ( 1 6 ( , 6 3 9 6 9 & 9 , 5 6 ) , & 2 0 3 , & 9 9 & & 9 6 3 9 & 2 0 3 9 5 6 ) 9 6 1 9 6 ( 1 6 ( 9 * 9 1 7 & 9 6 ' 2 9 / ( ' , 6 ( 1 6 ( , 3 : 0 b / 9 6 ( 1 6 ( 9 3 : 0 b / 9 6 ' , 9 & 6 1 9 0 2 8 7 , 0 2 8 7 , 3 : 0 , , 1 3 b 2 9 9 3 : 0 9 * , * , 6 1 , * 9 ( ; 7 9 & & , 1 5 ( 6 9 1 5 ( 6 , & & , 6 & . , 6 ' 2 , 6 ' , , & 6 1 9 , 1 3 b 2 9 9 / 0 2 ' ( , / 0 2 ' ( , 9 6 9 & & 9 ( 1 $ % / ( , ( 1 $ % / ( , * 1 ' * 1 ' , * 1 ' * 1 ' , 6 ( 1 6 ( , 6 1 1 7 & , 6 3 * * 9 / ( ' ( ; 7 b 9 & & , 6 ( 1 6 ( / 0 2 ' ( 9 / + 0 , / + 0 6 & . 6 ' 2 6 ' , 3 : 0 b / & 6 1 0 2 8 7 3 : 0 , 1 3 b 2 9 1 5 ( 6 ( 1 $ % / ( / + 0 , 9 / ( ' & 3 % 9 & & & 9 9 6 5 & & 2 0 3 5 6 ) 9 & & 6 & , 6 & 9 6 & * 1 ' , * 1 ' , & 3 % 9 & 3 % ( " 1 ( $ ' 5 table 15. absolute maximum ratings (1) symbol parameter value unit v s dc operating supply voltage 5.6 / 24 v v s_tr transient operating supply voltage (t < 400 ms) -0.3 / 40 v v sdi spi data input voltage range -0.3 / +5.3 v v sdo spi data output voltage range -0.3 / +5.3 v v sck spi clock voltage range -0.3 / +5.3 v v csn spi chip select not voltage range -0.3 /+5.3 v v nres reset output pin voltage range -0.3 v s +0.3 v v cc1 regulator1 supply voltage output -0.3 / + 5.5 v v cc2 regulator 2 supply voltage output -0.3 / + 10.5 v v enable enable input pin voltage range -0.3 v s +0.3 v v sc slope compensation input voltage range -0.3 / + 5.3 v docid025319 rev 1 45/69 L99LD01 electrical specifications 68 v lhm limp home mode input pin voltage range -0.3 v s +0.3 v v pwm input l.f. pwm voltage range -0.3 v s +0.3 v v pwm_l logic level l.f. pwm input voltage range -0.3 / +5.3 v v mout multiplexed data output pin voltage range -0.3 / +5.3 v v g1 driver 1 output voltage range -0.3 / (v cc2 + 0.3) v v g2 driver 2 gate output voltage range -0.3 / 70 v v ext_vcc external vcc voltage range -0.3 / 5.3 v v cpb external capacitor voltage range -0.3 / 70 v v isense + positive sensing res. voltage range -0.3 / 55 v v isense - negative sensing res. voltage range -0.3 / 55 v v sp sensing positive shunt res voltage range -0.3 / +5.3 v v sn sensing negative shunt res voltage range -0.3 / +5.3 v v inp_ov overvoltage input pin voltage range -0.3 v s +0.3 v v rsf external set frequency resistor voltage range -0.3 / 5.5 v v c5v c5v ext capacitor voltage range -0.3 / 5.5 v v rc comp external rc network input pin voltage range -0.3 / 5.5 v v ntc external ntc resistor input voltage range -0.3 / 5.5 v v led led chain drop voltage detection input range -0.3 / + 65 v v lmode led mode switch voltage range -0.3 / +5.3 v v esd electrostatic discharge (hbm r = 1.5 k ? ; c = 100 pf) 2 kv v esd cdm model all pin 500 v v esd cdm for corner pin 750 v tj junction operating temperature -40 to 150 c tstg storage temperature -55 to 150 c 1. maximum ratings are absolute ratings; exceeding any one of these values may cause permanent damage to the integrated circuit. table 15. absolute maximum ratings (1) (continued) symbol parameter value unit table 16. thermal data symbol parameter value unit r thj-case thermal resistance junction to case tbd c/w r thj-amb thermal resistance junction to ambient 90 c/w electrical characteristics L99LD01 46/69 docid025319 rev 1 5 electrical characteristics values specified in this section are for 5.6 v v s 24 v; -40 c tj 150 c, unless otherwise specified table 17. vs and v cc1 pin characteristics symbol parameter test condition min typ max unit v s operative battery voltage 5.6 24 v i s supply current consumption in continuous mode (l.f. pwm = 100 %) v s =13.5v; f req = 300 khz; i cc1 =i cc2 =i c5v =0 20 ma i s_stby supply current consumption in stand by mode enable = low; lhm,csn,pwm, inp_ov = open; v nres 5.5 v; v s =13.5v; t j =25oc 12 a v smin minimum v s required for reaching v cc1 nominal value v s ramp up 4.8 5.2 5.6 v v smin_hys v smin hysteresis v s ramp down 0.2 v t vsm v smin filtering time 13.5 16 18.5 s v cc1 d.c. logic supply output voltage 1 < -i cc1 <10ma 4.9 5 5.1 v -i cc1 output current capability v s =13.5v; v cc1 =v cc1_1ma - 0.1 v (1) 50 ma v cc1_drop drop voltage to v s: v cc1_drop =(v s - v cc1 ) -i cc1 =10ma 500 mv v cc1_line line regulation voltage -i cc1 = 10 ma; v cc1@5.6 ? v cc1@24 5mv v cc1_load load regulation voltage -i cc1 = 1 to 10 ma; v s = 13.5 v 10 mv v cc1_fail v cc1 fail detection threshold (2) v s v smin ; v cc1 rising 2.4 2.6 2.8 v v s v smin ; v cc1 falling 1.9 2.1 2.3 v t v1f internal filtering time for v cc1 fail detection v s v smin 1.7 2 2.3 s t shtv1a time to detect a short on v1 regulator at turn-on v s v smin ; v cc1 electrical characteristics L99LD01 50/69 docid025319 rev 1 table 24. i sense+ , i sense- pin, and o.t.a. characteristics symbol parameter test condition min typ max units vi sense+ir , vi sense-ir sensing resistor input voltage range 049v vi sense+ vi sense- common mode input range 049v (vi sense+ - vi sense- ) operative differential input voltage range -1 0.3 v (vi sense+ - vi sense- )_ th led over current protection threshold v(i sense +) = 25 v; v lref =v lref_16 ; v rccomp =2v v lref + 0.14 v lref + 0.18 v lref + 0.24 v i sense_cd current consumption from i sense+ (led_ov) v sense+ =v sense- =25v 3 5 10 ma v sense_max_1 threshold at pin i sense+ for overvoltage protection (activation) 49.5 52 55 v v sense_max_2 threshold at pin i sense+ for overvoltage protection (de- activation) 25 33 35 v v offs ota input offset voltage v lref = 0 v; v(i sense +) = 25 v; v rccomp =2v -10 10 mv i offs ota input offset current v(i sense +) = 25 v; v rccomp =2v 10 a g m transconductance gain v(i sense +) = 25 v; v rccomp =2v 0.95 1.2 ms -i comp sourced output current v lref =v lref_16 ; (vi sense+ - vi sense- )=0 50 175 a i comp sunk output current v lref =v lref_16 ; (vi sense+ - vi sense- ) = 300 mv 50 175 a v lref =v lref_16 ; (vi sense+ - vi sense- )=1v 100 300 v comp output voltage range 0 3.5 v v lref_16 default internal voltage reference for constant led current regulation internal led current register = 16d; v ntc =5v 142 150 158 mv v lref internal voltage reference range for setting output led current (1) v ntc =5v (8 + n) / 24 * v lref_16 (2) mv v lref_ntc max internal v lref reduction caused by ntc intervention (thermal led current reduction) v ntc =0v 0.5 * v lref mv docid025319 rev 1 51/69 L99LD01 electrical characteristics 68 v lref _ step internal voltage reference step 4 / 3 * (v lref_16 / 31) mv i sp , i sn pin characteristics v sp, v sn shunt resistor input voltage range -0.3 5 v v sp -v sn differential input voltage range -0.3 0.5 v g la_cpk gain of internal linear amplifier v sp = 100 mv; v sn =0v; pin sc floating 89.812 v la_offs linear amplifier output offset voltage v sp =v sn = 0 150 350 mv v cl_31 default internal reference for the current limiter (3) internal c.l. register = 31 3.5 v (v sp -v sn ) th differential threshold voltage for activate max input current prot. internal c.l. register = 31; v sc =5v 300 350 400 mv v cl internal c.l. voltage reference range 0.279 * v cl_31 v cl_31 v v cl_step internal c.l. voltage reference step (0.721 * v cl_31 / 31) v 1. writing into 5 bit led current register via spi. 2. n is the number corresponding to the 5 bits of led_curr control register. 3. settable by loading the 5 bit c.l. register via spi. table 24. i sense+ , i sense- pin, and o.t.a. characteristics (continued) symbol parameter test condition min typ max units table 25. sc pin characteristics symbol parameter test condition min typ max units v sc_low min ramp voltage at pin sc i sc =0; f o =300khz; i rsf =42a 0.12 0.2 0.3 v v sc_high max ramp voltage at pin sc i sc =0; f o =300khz; i rsf =42a 1.7 2 2.4 v r sc ext. resistor range 10 1000 k ? table 26. v led pin characteristics symbol parameter test condition min typ max units v led operative input voltage range for ov detection l mode =low 0 5 v l mode =high v s v s +5 electrical characteristics L99LD01 52/69 docid025319 rev 1 r vled _ pd pull down resistor 0.4 0.8 1.2 m ? ov_th1 led overvoltage threshold 1 boost application l mode = low 3.4 3.5 3.6 v ov_th2 led overvoltage threshold 2 boost application l mode = low 2.3 2.5 2.7 v ov_th1_vs led overvoltage threshold 1 buck-boost application l mode =high v s + 3.3 v s + 3.55 v s + 3.8 v ov_th2_vs led overvoltage threshold 2 buck-boost application l mode =high v s + 2.2 v s + 2.45 v s + 2.7 v table 26. v led pin characteristics (continued) symbol parameter test condition min typ max units table 27. inp_ov pin characteristics (input overvoltage shut down) symbol parameter test condition min typ max units v inp_ov operative input overvoltage range 0 5 v -i inp_ov pull up current source at input inp_ov v inp_ov =0v 10 18 25 a v inp_ov_th1 internal voltage reference 1 3.4 3.6 3.7 v v inp_ov_th2 internal voltage reference 2 2.7 2.9 3.1 v table 28. ntc pin characteristics symbol parameter test condition min typ max units v ntc operative ntc voltage range 0 5 v i ntc pull down current source v ntc =5 v 5 10 15 a v ntc_th1 reference for current led thermal regulation, temp ramp up led temp ramp up 1.13 1.2 1.27 v v ntc_th2 reference for current led thermal regulation, temp ramp down led temp ramp down 1.38 1.45 1.52 v table 29. enable, lhm pin characteristics symbol parameter test condition min typ max units v enable_l low level enable input voltage 1 v v enable_h high level enable input voltage 4 v r enable_pd enable pull down resistor 50 250 500 k ? v lhm_l low level limp home mode input pin 1 v v lhm_h high level limp home mode input pin 4 v i lhm_pu limp home pin pull up current v hlm = 0 10 18 25 a docid025319 rev 1 53/69 L99LD01 electrical characteristics 68 table 30. power on reset symbol parameter test condition min typ max units por_ th1 internal power on reset threshold v c5v rising; v s =13.5v; c5v = 10 f 3.2 3.7 4.2 v por_ th2 internal power on reset threshold v c5v falling; v s = 13.5 v; c5v = 10 f 2.7 3.4 3.7 v table 31. watchdog and timers parameters symbol parameter test condition min typ max units t wdto watchdog timeout window 100 or 200 (1) ms t dstart start time window 5 ms t enrecov 5ms 1. selectable by spi command. spi electrical characteristics L99LD01 54/69 docid025319 rev 1 6 spi electrical characteristics 6.1 dc characteristics the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v s 24 v; all outputs open; t j = -40 c to 150 c, unless otherwise specified. 6.2 ac characteristics the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v s 24 v; all outputs open; t j = -40 c to 150 c, unless otherwise specified. table 32. spi dc characteristics symbol parameter test condition min typ max unit inputs: csn, clk, di v il input voltage low level v s =13.5v 0.3 v c5v v v ih input voltage high level v s =13.5v 0.7 v c5v v v ihys input hysteresis v s = 13.5 v 500 mv i csn in csn pull-up current source v s = 13.5 v 10 18 25 a i clk in clk pull-down current source v s = 13.5 v 20 25 30 a i di in di pull-down current source v s = 13.5 v 20 25 30 a output: do v ol output voltage low level i ol =5ma; v s =13.5v 0.3 v c5v v v oh output voltage high level i oh =-5ma; v s =13.5v 0.7 v c5v v table 33. spi ac characteristics symbol parameter test condition min typ max unit c out (1) 1. value of input capacity is not measured in production test. parameter guaranteed by design. output capacitance (do) ? ? 10 pf c in (1) input capacitance (di, csn, clk) ? ? 10 pf docid025319 rev 1 55/69 L99LD01 spi electrical characteristics 68 6.3 dynamic characteristics the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v s 24 v; all outputs open; t j = -40 c to 150 c, unless otherwise specified. for definition of the parameters please see figure 29 and figure 30 . table 34. spi dynamic characteristics symbol parameter test condition min typ max unit t csnqvl do enable from tristate to low level cdo = 100 pf; i do =1ma; pull-up load to v cc ; v cc1 =5.0v 100 250 ns t csnqvh do enable from tristate to high level cdo = 100 pf; i do =- 1 ma; pull-down load to gnd; v cc1 =5.0v 100 250 ns t csnqtl do disable from low level to tristate c do = 100 pf; i do =4ma; pull-up load to v cc ; v cc1 =5.0v 380 450 ns t csnqth do disable from high level to tristate c do = 100 pf, i do = -4 ma; pull-down load to gnd; v cc1 =5.0v 380 450 ns t clkqv clk falling until do valid v do <0.3v cc or v do >0.7v cc ; c do =5pf; v cc1 =5.0v ns v do <0.3v cc or v do >0.7v cc ; c do = 100 pf; v cc1 =5.0v ns t scsn csn setup time, csn low before rising edge of clk v cc1 = 5.0 v 400 ns t sdi di setup time, di stable before rising edge of clk v cc1 = 5.0 v 200 ns t hclk minimum clk high time v cc1 = 5.0 v 115 ns t lclk minimum clk low time v cc1 = 5.0 v 115 ns t hcsn minimum csn high time v cc1 =5.0v 4 s t sclk clk setup time before csn rising v cc1 = 5.0 v 400 ns t r do do rise time c do = 100 pf; v cc1 = 5.0 v 80 140 ns t f do do fall time c do = 100 pf; v cc1 = 5.0 v 50 100 ns t r in rise time of input signal di, clk, csn v cc1 = 5.0 v 100 ns t f in fall time of input signal di, clk, csn v cc1 = 5.0 v 100 ns spi electrical characteristics L99LD01 56/69 docid025319 rev 1 figure 29. spi timing parameters figure 30. spi input and output timing parameters & 6 1 ' 2 ' d w d r x w w & 6 1 4 7 w & / . 4 9 & / . ' d w d r x w w + & / . w / & / . w 6 & 6 1 w + & 6 1 ' d w d l q ' d w d l q w 6 ' , ' , w & 6 1 4 9 w 6 & / . ( " 1 ( $ ' 5 ' 2 o r z w r k l j k 9 & & 9 & & w u ' 2 ' 2 k l j k w r o r z 9 & & 9 & & w i ' 2 w i l q w u l q ' , & / . & 6 1 9 & & 9 & & ( " 1 ( $ ' 5 docid025319 rev 1 57/69 L99LD01 spi electrical characteristics 68 figure 31. spi maximum clock frequency the maximum spi clock frequency can be calculated as follows (see figure 31 ): t clkqv (total) = t clkrise (uc) + t clkfilt (pcb) + t clkqv (slave) + t setup (uc) f clk (max) < ? x t clkqv (total) example: t clkqv = 25 ns + 100 ns + 250 ns + 25 ns = 400 ns f clk (max) < 1.25 mhz figure 32. nres pin open drain structure 0 l f u r & r q w u r o o h u 0 d v w h u 6 o d y h 6 & . 0 , 6 2 w 6 & . u l v h w 6 & . i l o w w 6 & . 4 9 w v h w x s ( " 1 ( $ ' 5 1 5 ( 6 1 5 ( 6 ( " 1 ( $ ' 5 spi electrical characteristics L99LD01 58/69 docid025319 rev 1 figure 33. handshake procedure at start up with microcontroller on board 1 5 ( 6 p v 6 w d u w x s $ f n q r z o h g j p h q w z l w k l q r u p v p v , i q r d f n q r z o h g j p h q w z l w k l q r u p v ? g h y l f h h q w h u v l q / l p s + r p h p r g h , i q r d f n q r z o h g j p h q w d i w h u f r q v h f x w l y h u h v h w s x o v h v g h y l f h h q w h u v l q / l p s + r p h 0 r g h d q g 5 h j x o d w r u 9 & & l v v z l w f k h g 2 ) ) 6 w d u w x s d f n q r z o h g j p h q w z l w k l q r w k h u r u p v p v 1 5 ( 6 9 & & 9 & & b 7 + 1 5 ( 6 ( " 1 ( $ ' 5 docid025319 rev 1 59/69 L99LD01 application circuits 68 7 application circuits typical application circuits are shown on the following figure 34 , figure 35 and figure 36 . figure 37 shows the case of standalone application. figure 38 shows an example for the boost converter topology which uses an external mosfet m3, for provide reverse battery protection, maintaining at same time a very low drop voltage in the normal functioning, but achieving low dissipation and high efficiency, in case of high power applications (led headlamps). figure 34. boost application circuit 6 x s s o \ y r o w d j h s u r y l g h g e \ w k h e r g \ f r q w u r o p r g x o h & k d v w r e h x v h g l q f d v h w k h g h i d x o w p v u h v h w w l p h k d v w r e h l q f u h d v h g , q f d v h r i / l p s + r p h h y h q w / + 0 j q g ? ' h y l f h d o z d \ v 2 i i / + 0 2 s h q r u + l j k ? ' h y l f h d o z d \ v 2 1 ( ; 7 b 9 & & & r q q h f w w k l v s l q w r j q g l i w k h x 3 l v v x s s o l h g e \ 9 & & s l q , i w k h x 3 l v h [ w h u q d o o \ v x s s o l h g e \ d q h [ w h u q d o 9 v x s s o \ f r q q h f w w k l v s l q w r w k h x 3 h [ w h u q d o v x s s o \ 5 & f r p s r q h q w v k d y h w r e h f k r v h q l q r u g h u w r g r q ? w u h v h w w k h g h y l f h g x u l q j 3 : 0 r s h u d w h g e \ w k h % & 0 9 r o w d j h 2 s w l r q d o f r p s r q h q w v i r u q r l v \ i l o w h u l q j 9 % & 0 5 5 5 1 7 & 5 5 6 ( 1 6 ( 5 6 + 8 1 7 & & & & 0 0 5 5 & 0 l f u r 9 & & ' 5 5 5 & & 5 9 6 5 & f r p s 6 ' , 5 6 ) & 9 3 : 0 b / 6 ' 2 6 & . * 1 7 & , v h q v h , v h q v h 9 & & 9 / ( ' 9 & & * q g ( ; 7 b 9 & & * q g , 6 3 , 6 1 & 6 1 0 2 8 7 3 : 0 , 1 3 b 2 9 / 0 2 ' ( 1 5 ( 6 ( 1 $ % / ( * / + 0 * q g 6 & & 3 % 5 5 & ' . . . . q ) q ) . ( " 1 ( $ ' 5 application circuits L99LD01 60/69 docid025319 rev 1 figure 35. fly back application circuit 6 x s s o \ y r o w d j h s u r y l g h g e \ w k h e r g \ f r q w u r o p r g x o h & k d v w r e h x v h g l q f d v h w k h g h i d x o w p v u h v h w w l p h k d v w r e h l q f u h d v h g , q f d v h r i / l p s + r p h h y h q w / + 0 j q g ? ' h y l f h d o z d \ v 2 i i / + 0 2 s h q r u + l j k ? ' h y l f h d o z d \ v 2 1 ( ; 7 b 9 & & & r q q h f w w k l v s l q w r j q g l i w k h x 3 l v v x s s o l h g e \ 9 & & s l q , i w k h x 3 l v h [ w h u q d o o \ v x s s o l h g e \ d q h [ w h u q d o 9 v x s s o \ f r q q h f w w k l v s l q w r w k h x 3 h [ w h u q d o v x s s o \ 5 & f r p s r q h q w v k d y h w r e h f k r v h q l q r u g h u w r g r q ? w u h v h w w k h g h y l f h g x u l q j 3 : 0 r s h u d w h g e \ w k h % & 0 9 r o w d j h 2 s w l r q d o f r p s r q h q w v i r u q r l v \ i l o w h u l q j & 5 5 5 1 7 & 5 5 6 ( 1 6 ( 5 6 + 8 1 7 & & & & 0 0 5 5 0 l f u r 5 & 5 5 & 5 5 & 9 % & 0 ' & & 5 9 6 5 & f r p s 6 ' , 5 6 ) & 9 3 : 0 b / 6 ' 2 6 & . * 1 7 & , v h q v h , v h q v h 9 & & 9 / ( ' 9 & & * q g ( ; 7 b 9 & & * q g , 6 3 , 6 1 & 6 1 0 2 8 7 3 : 0 , 1 3 b 2 9 / 0 2 ' ( 1 5 ( 6 ( 1 $ % / ( * / + 0 * q g 6 & & 3 % 9 5 & ' . . . . q ) q ) . ( " 1 ( $ ' 5 docid025319 rev 1 61/69 L99LD01 application circuits 68 figure 36. buck-boost application circui t 6 x s s o \ y r o w d j h s u r y l g h g e \ w k h e r g \ f r q w u r o p r g x o h & k d v w r e h x v h g l q f d v h w k h g h i d x o w p v u h v h w w l p h k d v w r e h l q f u h d v h g , q f d v h r i / l p s + r p h h y h q w / + 0 j q g ? ' h y l f h d o z d \ v 2 i i / + 0 2 s h q r u + l j k ? ' h y l f h d o z d \ v 2 1 ( ; 7 b 9 & & & r q q h f w w k l v s l q w r j q g l i w k h x 3 l v v x s s o l h g e \ 9 & & s l q , i w k h x 3 l v h [ w h u q d o o \ v x s s o l h g e \ d q h [ w h u q d o 9 v x s s o \ f r q q h f w w k l v s l q w r w k h x 3 h [ w h u q d o v x s s o \ 5 & f r p s r q h q w v k d y h w r e h f k r v h q l q r u g h u w r g r q ? w u h v h w w k h g h y l f h g x u l q j 3 : 0 r s h u d w h g e \ w k h % & 0 9 r o w d j h 2 s w l r q d o f r p s r q h q w v i r u q r l v \ i l o w h u l q j & 5 5 5 6 ( 1 6 ( 5 6 + 8 1 7 & & & 0 0 5 5 5 5 0 l f u r 5 & 5 1 7 & 5 5 & 9 % & 0 ' & & 5 9 6 5 & f r p s 6 ' , 5 6 ) & 9 3 : 0 b / 6 ' 2 6 & . * 1 7 & , v h q v h , v h q v h 9 & & 9 / ( ' 9 & & * q g ( ; 7 b 9 & & * q g , 6 3 , 6 1 & 6 1 0 2 8 7 3 : 0 , 1 3 b 2 9 / 0 2 ' ( 1 5 ( 6 ( 1 $ % / ( * / + 0 * q g 6 & & 3 % 9 5 & ' . . . . q ) q ) & . ( " 1 ( $ ' 5 application circuits L99LD01 62/69 docid025319 rev 1 figure 37. stand alone application example for boost topology 6 x s s o \ y r o w d j h s u r y l g h g e \ w k h e r g \ f r q w u r o p r g x o h 7 k h l q w h u q d o f l u f x l w u \ u h f r j q l ] h v w k h v w d q g d o r q h r s h u d w l r q v k r u w l q j 1 5 ( 6 w r 9 6 & r q q h f w w k l v s l q w r 9 i r u h q d e o l q j ' l w k h u ( i i h f w ( ; 7 b 9 & & , q v w d q g d o r q h l v v x j j h v w h g w r f r q q h f w w k l v s l q w r & 9 5 & f r p s r q h q w v k d y h w r e h f k r v h q l q r u g h u w r g r q ? w u h v h w w k h g h y l f h g x u l q j 3 : 0 r s h u d w h g e \ w k h % & 0 9 r o w d j h 2 s w l r q d o f r p s r q h q w v i r u q r l v \ i l o w h u l q j 9 % & 0 5 5 5 5 5 1 7 & 5 5 6 ( 1 6 ( 5 6 + 8 1 7 & & 0 0 5 5 5 & ' & 5 & & & 5 . & 9 6 5 & f r p s 6 ' , 5 6 ) & 9 3 : 0 b / 6 ' 2 6 & . * 1 7 & , v h q v h , v h q v h 9 & & 9 / ( ' 9 & & * q g ( ; 7 b 9 & & * q g , 6 3 , 6 1 & 6 1 0 2 8 7 3 : 0 , 1 3 b 2 9 / 0 2 ' ( 1 5 ( 6 ( 1 $ % / ( * / + 0 * q g 6 & & 3 % 9 5 & ' q ) q ) . ( " 1 ( $ ' 5 docid025319 rev 1 63/69 L99LD01 application circuits 68 figure 38. reverse battery protection: an example for boost topology if the drl module is supplied by a high side driver (hsd) of the body control module (bcm), a minimum current consumption is requested during the off phase of the pwm dimming, so that the hsd of the bcm do not detect a wrong open load condition. this is in charge of the p which has to draw this ?minimum current consumption?, from the supply line (see figure 39 ). & k d v w r e h x v h g l q f d v h w k h g h i d x o w p v u h v h w w l p h k d v w r e h l q f u h d v h g , q f d v h r i / l p s + r p h h y h q w / + 0 j q g ? ' h y l f h d o z d \ v 2 i i / + 0 2 s h q r u + l j k ? ' h y l f h d o z d \ v 2 1 ( ; 7 b 9 & & & r q q h f w w k l v s l q w r j q g l i w k h x 3 l v v x s s o l h g e \ 9 & & s l q , i w k h x 3 l v h [ w h u q d o o \ v x s s o l h g e \ d q h [ w h u q d o 9 v x s s o \ f r q q h f w w k l v s l q w r w k h x 3 h [ w h u q d o v x s s o \ 2 s w l r q d o f r p s r q h q w v i r u q r l v \ i l o w h u l q j 9 % $ 7 7 5 5 & r q w u r o & 5 5 5 1 7 & 5 5 6 ( 1 6 ( 5 6 + 8 1 7 & & & & 0 0 0 5 5 0 l f u r 5 & ( q d e o h & r q w u r o 5 & & & 5 9 6 5 & f r p s 6 ' , 5 6 ) & 9 3 : 0 b / 6 ' 2 6 & . * 1 7 & , v h q v h , v h q v h 9 & & 9 / ( ' 9 & & * q g ( ; 7 b 9 & & * q g , 6 3 , 6 1 & 6 1 0 2 8 7 3 : 0 , 1 3 b 2 9 / 0 2 ' ( 1 5 ( 6 ( 1 $ % / ( * / + 0 * q g 6 & & 3 % 9 . . . . q ) q ) . ( " 1 ( $ ' 5 application circuits L99LD01 64/69 docid025319 rev 1 figure 39. external mos required during pwm dimming 0 l v w x u q h g r q g x u l q j w k h r i i s k d v h r i w k h 3 : 0 b / g l p p l q j v l j q d o 0 9 % & 0 & 0 l f u r ' 3 : 0 b / g l p p l q j h j g x w \ f \ f o h 6 d p h r u p x o w l s o h i u h t x h q f \ r i 9 % & 0 p r g x o d w l r q 7 r 3 : 0 b / s l q r i / ( ' g u l y h u 9 r o w d j h p r g x o d w l r q z l w k k l j k g x w \ f \ f o h + ] s u r y l g h g e \ w k h + 6 ' r i w k h % r g \ & r q w u r o 0 r g x o h ' ! 0 ' # & 4 docid025319 rev 1 65/69 L99LD01 package information 68 8 package information 8.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 8.2 lqfp32? package information figure 40. lqfp32? package dimensions package information L99LD01 66/69 docid025319 rev 1 table 35. lqfp32? mechanical data symbol millimeters min. typ. max. a 1.6 a1 0.05 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 c0.09 0.20 d9.00 d1 7.00 d3 5.60 e0.80 e9.00 e1 7.00 e3 5.60 l 0.45 0.60 0.75 l1 1.00 k0 3.5 7 docid025319 rev 1 67/69 L99LD01 order codes 68 9 order codes table 36. device summary package order code tube lqfp32 L99LD01 revision history L99LD01 68/69 docid025319 rev 1 10 revision history table 37. document revision history date revision changes 19-jun-2014 1 initial release. docid025319 rev 1 69/69 L99LD01 69 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com |
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